Architecture 2.0 Living registry
Tool registry

Tool registry

The action space for AI-assisted architecture

The tools below make up the working environment an architecture design loop operates in: the simulators and proxy models that supply feedback, the verification harnesses, benchmarks, and datasets that supply evidence, and the data representations that let a loop read and write a design. Each entry should make its role in the loop visible, so the registry stays an architecture agenda rather than a general list of interesting projects.

The registry is community-maintained. If you have built an open-source simulator, surrogate model, verification harness, or agentic workflow, you can propose it for the registry. Submissions include authors, institutions, papers, artifact status, tags, and a short fit note for maintainers. The public card keeps the visible information compact: summary, credit, category, and tags.

gem5

Modular computer-system simulator for architecture feedback needing workload execution and reproducible state.

N. Binkert, B. Beckmann et al. gem5 community
Simulation simulation full-system reproducibility

FireSim

FPGA-accelerated full-system simulation for when the loop needs stronger hardware/software feedback than a proxy can provide.

S. Karandikar, H. Mao et al. UC Berkeley
Simulation simulation FPGA hardware/software

Chipyard

Integrated framework for generating and evaluating hardware systems, connecting generators, RTL, and simulation.

A. Amid, D. Biancolin et al. UC Berkeley
Simulation RTL generation simulation SoC

SST

Modular parallel simulation framework for exploring systems where ISA, microarchitecture, memory, programming model, and communication interact.

A. Rodrigues, K. S. Hemmert et al. Sandia National Laboratories
Simulation parallel simulation memory systems HPC

ChampSim

Trace-based simulator for fast feedback on cache, branch prediction, prefetching, and memory-hierarchy ideas.

ChampSim contributors Texas A&M / community
Simulation trace simulation microarchitecture memory hierarchy

GPGPU-Sim

Detailed GPU simulator for CUDA and OpenCL workloads when a loop needs microarchitectural feedback for GPU designs.

A. Bakhoda, G. Yuan et al. University of British Columbia
Simulation GPU CUDA microarchitecture

Sniper

Fast multicore x86 simulator based on interval core modeling for many-core architecture tradeoff studies.

T. Carlson, W. Heirman et al. Ghent University
Simulation multicore x86 interval simulation

zsim

Fast x86-64 multicore simulator focused on memory hierarchies and large heterogeneous systems.

D. Sanchez, C. Kozyrakis MIT / Stanford
Simulation x86-64 memory hierarchy heterogeneous systems

Ramulator 2.0

Modular cycle-accurate DRAM simulator for evaluating memory-system designs, DRAM standards, and mitigation ideas.

H. Luo, Y. C. Tugrul et al. CMU SAFARI Research Group
Simulation DRAM memory systems cycle-accurate

DRAMsim3

Cycle-accurate, thermal-capable DRAM simulator supporting DDR, LPDDR, GDDR, HBM, HMC, and related protocols.

S. Li, Z. Yang et al. University of Maryland
Simulation DRAM thermal modeling memory protocols

BookSim

Cycle-accurate interconnection-network simulator for studying NoC topologies, routing, and router microarchitecture.

N. Jiang, D. U. Becker et al. Stanford / LBNL
Simulation NoC interconnects routing

SCALE-Sim

Systolic-array accelerator simulator for quickly exploring DNN accelerator design spaces.

A. Samajdar, Y. Zhu et al. Georgia Tech / Arm
Simulation systolic arrays DNN accelerators design space exploration

Verilator

The fastest free Verilog HDL simulator, converting Verilog to C++/SystemC.

W. Snyder et al. Veripool / community
Simulation Verilog simulation SystemC

Apollo

An automated framework for fast, accurate, and transferable architecture design space exploration using surrogate models.

A. Yazdanbakhsh, C. Angermueller et al. Google Research
Proxy Models surrogate models design space exploration ML

Aladdin

Pre-RTL power and performance simulator for accelerator-centric design-space exploration.

Y. S. Shao, B. Reagen et al. Harvard / UC Berkeley
Proxy Models accelerators pre-RTL design space exploration

MAESTRO

Analytical cost model for DNN dataflows and tiling; a fast-feedback model for dataflow exploration.

H. Kwon, P. Chatarasi et al. Georgia Tech
Proxy Models cost modeling DNN accelerators dataflows

Accelergy

Energy-estimation infrastructure for accelerators, providing an explicit energy feedback source.

Y. N. Wu, J. S. Emer et al. MIT / NVIDIA
Proxy Models energy modeling accelerators

Timeloop

Mapping and modeling tool for tensor workloads on accelerator architectures.

A. Parashar, P. Raina et al. NVIDIA / MIT
Proxy Models mapping tensor workloads accelerators

McPAT

Power, area, and timing modeling framework for multicore and manycore architectures.

S. Li, J. H. Ahn et al. HP Labs / UC San Diego
Proxy Models power modeling area modeling manycore

CACTI

Analytical model for cache and memory access time, cycle time, area, and power.

N. Muralimanohar, R. Balasubramonian et al. HP Labs / University of Utah
Proxy Models cache modeling memory modeling power

ArchGym

Open-source gym environment for evaluating machine learning algorithms in computer architecture exploration.

S. Krishnan, A. Yazdanbakhsh et al. Harvard / Google Research
Agentic Workflows reinforcement learning design space exploration

AutoChip

Conversational hardware design using LLMs to generate Verilog from natural language specifications.

S. Thakur, J. Blocklove et al. NYU
Agentic Workflows LLMs Verilog automation

ChipNeMo

Domain-adapted LLMs for chip design, demonstrating automated EDA script generation and bug analysis.

M. Liu, T. Ene et al. NVIDIA
Agentic Workflows LLMs EDA scripts chip design

VeriGen

A large language model customized for generating functional Verilog code.

S. Thakur, B. Ahmad et al. NYU / University of Calgary
Agentic Workflows LLMs Verilog code generation

Chisel

A hardware construction language embedded in Scala that provides high-level primitives for RTL generation.

J. Bachrach, H. Vo et al. UC Berkeley
Data Representations hardware construction Scala RTL

PyMTL3

An open-source Python-based hardware generation and simulation framework.

S. Jiang, P. Pan et al. Cornell University
Data Representations Python hardware modeling simulation

FIRRTL

A flexible intermediate representation for RTL, serving as the bridge between high-level generators and EDA tools.

A. Izraelevitz, J. Koenig et al. UC Berkeley / CHIPS Alliance
Data Representations IR RTL compiler infrastructure

CocoTB

A coroutine-based cosimulation library for writing VHDL and Verilog testbenches in Python.

S. Hodgson, C. Higgs et al. FOSSi Foundation / community
Verification testbenches Python cosimulation

SymbiYosys

Front-end for Yosys-based formal verification flows, allowing agents to assert mathematical proofs against their generated RTL.

C. X. Wolf et al. YosysHQ / community
Verification formal verification RTL Yosys

CVDP Benchmark

Comprehensive Verilog Design Problems for RTL design and verification. Crucial for loops involving HDL generation and test harnesses.

N. Pinckney, C. Deng et al. NVIDIA
Benchmarks and Datasets Verilog benchmarks verification

RTLLM

Benchmark for natural-language-to-RTL generation with Verilog designs, descriptions, and testbenches.

Y. Lu, S. Liu et al. HKUST
Benchmarks and Datasets Verilog LLMs RTL generation

RTL-Repo

Benchmark for evaluating LLMs on Verilog code completion within larger RTL repositories.

A. Allam, M. Shalan AUCOHL
Benchmarks and Datasets Verilog code completion repository context

MLPerf Inference

MLCommons benchmark suite for measuring how fast systems run trained models across deployment scenarios.

MLCommons contributors MLCommons
Benchmarks and Datasets ML systems inference performance

QuArch

Architecture question-answering and reasoning benchmark to test if a model can reason over architecture concepts.

S. Prakash, A. Cheng et al. Harvard / Google Research
Benchmarks and Datasets reasoning benchmark architecture QA

VerilogEval

Specification-to-RTL and Verilog code-generation benchmark with executable checks.

M. Liu, N. Pinckney et al. NVIDIA
Benchmarks and Datasets Verilog code generation correctness

KernelBench

GPU-kernel generation benchmark with correctness and performance evaluation.

A. Ouyang, S. Guo et al. Stanford
Benchmarks and Datasets GPU kernels correctness performance

CircuitNet

VLSI CAD dataset for machine-learning applications in EDA.

Z. Chai, Y. Zhao et al. Peking University / Wuhan University
Benchmarks and Datasets VLSI CAD datasets EDA

OpenROAD

Open-source RTL-to-GDS flow for loops that need physical-design feedback and evidence.

T. Ajayi, V. Chhabria et al. The OpenROAD Project
Physical Design RTL-to-GDS physical design open source EDA

ChiPBench

Benchmark focused on end-to-end physical-design impact for AI chip placement.

Z. Wang, Z. Geng et al. USTC / Alibaba
Physical Design placement physical design benchmark
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