# Frozen Architecture 2.0 print-release registry snapshot, 2026-07-14. # Source: tools/tools.yml at the release-readiness freeze; do not edit in place. # Generated by .github/scripts/build_catalog_index.py from tools/registry/*.yml. - title: gem5 url: https://www.gem5.org/ artifact_type: Tool categories: - Simulation description: Modular computer-system simulator for architecture feedback needing workload execution and reproducible state. fit_note: Provides executable system state and performance feedback when a loop needs detailed architecture simulation. authors: N. Binkert, B. Beckmann et al. institution: gem5 community order: 1 artifact_availability: source_available last_verified: 2026-07-10 tags: - simulation - full-system - reproducibility source_file: gem5.yml - title: FireSim url: https://fires.im/ artifact_type: Tool categories: - Simulation description: FPGA-accelerated full-system simulation for when the loop needs stronger hardware/software feedback than a proxy can provide. fit_note: Supplies FPGA-backed cycle-exact feedback for loops that need stronger evidence than software simulation. authors: S. Karandikar, H. Mao et al. institution: UC Berkeley order: 2 artifact_availability: source_available last_verified: 2026-07-10 tags: - simulation - FPGA - hardware/software source_file: firesim.yml - title: Chipyard url: https://chipyard.readthedocs.io/ artifact_type: Tool categories: - Simulation description: Integrated framework for generating and evaluating hardware systems, connecting generators, RTL, and simulation. fit_note: Connects generators, RTL, simulation, and software so loops can move from architectural intent to evaluable systems. authors: A. Amid, D. Biancolin et al. institution: UC Berkeley order: 3 artifact_availability: source_available last_verified: 2026-07-10 tags: - RTL generation - simulation - SoC source_file: chipyard.yml - title: SST url: https://sst-simulator.org/ artifact_type: Tool categories: - Simulation description: Modular parallel simulation framework for exploring systems where ISA, microarchitecture, memory, programming model, and communication interact. fit_note: Models large-scale system behavior when loops need component-level interaction and scalability evidence. authors: A. Rodrigues, K. S. Hemmert et al. institution: Sandia National Laboratories order: 4 artifact_availability: source_available last_verified: 2026-07-10 tags: - parallel simulation - memory systems - HPC source_file: sst.yml - title: ChampSim url: https://github.com/ChampSim/ChampSim artifact_type: Tool categories: - Simulation description: Trace-based simulator for fast feedback on cache, branch prediction, prefetching, and memory-hierarchy ideas. fit_note: Supports microarchitecture exploration with trace-driven feedback for cache, branch, and memory-system ideas. authors: ChampSim contributors institution: Texas A&M / community order: 5 artifact_availability: source_available last_verified: 2026-07-10 tags: - trace simulation - microarchitecture - memory hierarchy source_file: champsim.yml - title: GPGPU-Sim url: https://github.com/gpgpu-sim/gpgpu-sim_distribution artifact_type: Tool categories: - Simulation description: Detailed GPU simulator for CUDA and OpenCL workloads when a loop needs microarchitectural feedback for GPU designs. fit_note: Provides GPU architecture simulation feedback for loops exploring throughput, memory, and parallel execution tradeoffs. authors: A. Bakhoda, G. Yuan et al. institution: University of British Columbia order: 6 artifact_availability: source_available last_verified: 2026-07-10 tags: - GPU - CUDA - microarchitecture source_file: gpgpu-sim.yml - title: Sniper url: https://snipersim.org/ artifact_type: Tool categories: - Simulation description: Fast multicore x86 simulator based on interval core modeling for many-core architecture tradeoff studies. fit_note: Supplies fast multicore simulation feedback for loops comparing core counts, cache hierarchies, and parallel workloads. authors: T. Carlson, W. Heirman et al. institution: Ghent University order: 7 artifact_availability: source_available last_verified: 2026-07-10 tags: - multicore - x86 - interval simulation source_file: sniper.yml - title: zsim url: https://github.com/s5z/zsim artifact_type: Tool categories: - Simulation description: Fast x86-64 multicore simulator focused on memory hierarchies and large heterogeneous systems. fit_note: Supports fast many-core architecture feedback when loops need scalable timing estimates across large design spaces. authors: D. Sanchez, C. Kozyrakis institution: MIT / Stanford order: 8 artifact_availability: source_available last_verified: 2026-07-10 tags: - x86-64 - memory hierarchy - heterogeneous systems source_file: zsim.yml - title: Ramulator 2.0 url: https://github.com/CMU-SAFARI/ramulator2 artifact_type: Tool categories: - Simulation description: Modular cycle-accurate DRAM simulator for evaluating memory-system designs, DRAM standards, and mitigation ideas. fit_note: Gives memory-system loops a configurable DRAM model for testing scheduling, timing, and workload sensitivity. authors: H. Luo, Y. C. Tugrul et al. institution: CMU SAFARI Research Group order: 9 artifact_availability: source_available last_verified: 2026-07-10 tags: - DRAM - memory systems - cycle-accurate source_file: ramulator-2.yml - title: DRAMsim3 url: https://github.com/umd-memsys/DRAMsim3 artifact_type: Tool categories: - Simulation description: Cycle-accurate, thermal-capable DRAM simulator supporting DDR, LPDDR, GDDR, HBM, HMC, and related protocols. fit_note: Provides detailed DRAM feedback for architecture loops that need memory timing and power estimates. authors: S. Li, Z. Yang et al. institution: University of Maryland order: 10 artifact_availability: source_available last_verified: 2026-07-10 tags: - DRAM - thermal modeling - memory protocols source_file: dramsim3.yml - title: BookSim url: https://github.com/booksim/booksim2 artifact_type: Tool categories: - Simulation description: Cycle-accurate interconnection-network simulator for studying NoC topologies, routing, and router microarchitecture. fit_note: Models network-on-chip behavior so loops can evaluate topology, routing, and traffic design choices. authors: N. Jiang, D. U. Becker et al. institution: Stanford / LBNL order: 11 artifact_availability: source_available last_verified: 2026-07-10 tags: - NoC - interconnects - routing source_file: booksim.yml - title: SCALE-Sim url: https://github.com/scalesim-project/SCALE-Sim artifact_type: Tool categories: - Simulation description: Systolic-array accelerator simulator for quickly exploring DNN accelerator design spaces. fit_note: Offers systolic-array feedback for accelerator loops that need fast mapping, utilization, and bandwidth estimates. authors: A. Samajdar, Y. Zhu et al. institution: Georgia Tech / Arm order: 12 artifact_availability: source_available last_verified: 2026-07-10 tags: - systolic arrays - DNN accelerators - design space exploration source_file: scale-sim.yml - title: Verilator url: https://www.veripool.org/verilator/ artifact_type: Tool categories: - Simulation description: The fastest free Verilog HDL simulator, converting Verilog to C++/SystemC. fit_note: Turns RTL into executable models so loops can test generated or modified hardware designs quickly. authors: W. Snyder et al. institution: Veripool / community order: 13 artifact_availability: source_available last_verified: 2026-07-10 tags: - Verilog - simulation - SystemC source_file: verilator.yml - title: Apollo url: https://arxiv.org/abs/2102.01723 artifact_type: Design Loop categories: - Proxy Models description: An automated framework for fast, accurate, and transferable architecture design space exploration using surrogate models. fit_note: Uses transferable surrogate modeling to guide accelerator exploration with fewer expensive evaluations. authors: A. Yazdanbakhsh, C. Angermueller et al. institution: Google Research order: 14 artifact_availability: paper_only last_verified: 2026-07-10 tags: - surrogate models - design space exploration - ML source_file: apollo.yml - title: Aladdin url: https://github.com/harvard-acc/ALADDIN artifact_type: Tool categories: - Proxy Models description: Pre-RTL power and performance simulator for accelerator-centric design-space exploration. fit_note: Provides pre-RTL accelerator estimates so loops can reject weak designs before detailed implementation. authors: Y. S. Shao, B. Reagen et al. institution: Harvard / UC Berkeley order: 15 artifact_availability: source_available last_verified: 2026-07-10 tags: - accelerators - pre-RTL - design space exploration source_file: aladdin.yml - title: MAESTRO url: https://github.com/maestro-project/maestro artifact_type: Tool categories: - Proxy Models description: Analytical cost model for DNN dataflows and tiling; a fast-feedback model for dataflow exploration. fit_note: Analyzes DNN dataflows and mappings so loops can compare accelerator performance and energy tradeoffs. authors: H. Kwon, P. Chatarasi et al. institution: Georgia Tech order: 16 artifact_availability: source_available last_verified: 2026-07-10 tags: - cost modeling - DNN accelerators - dataflows source_file: maestro.yml - title: Accelergy url: https://github.com/Accelergy-Project/accelergy artifact_type: Tool categories: - Proxy Models description: Energy-estimation infrastructure for accelerators, providing an explicit energy feedback source. fit_note: Supplies architecture-level energy estimates for loops that need explicit cost evidence across design choices. authors: Y. N. Wu, J. S. Emer et al. institution: MIT / NVIDIA order: 17 artifact_availability: source_available last_verified: 2026-07-10 tags: - energy modeling - accelerators source_file: accelergy.yml - title: Timeloop url: https://github.com/NVlabs/timeloop artifact_type: Tool categories: - Proxy Models description: Mapping and modeling tool for tensor workloads on accelerator architectures. fit_note: Explores DNN accelerator mapspaces and topologies when loops need performance and energy feedback. authors: A. Parashar, P. Raina et al. institution: NVIDIA / MIT order: 18 artifact_availability: source_available last_verified: 2026-07-10 tags: - mapping - tensor workloads - accelerators source_file: timeloop.yml - title: McPAT url: https://github.com/HewlettPackard/mcpat artifact_type: Tool categories: - Proxy Models description: Power, area, and timing modeling framework for multicore and manycore architectures. fit_note: Provides power, area, and timing estimates for processor architecture loops comparing system-level tradeoffs. authors: S. Li, J. H. Ahn et al. institution: HP Labs / UC San Diego order: 19 artifact_availability: source_available last_verified: 2026-07-10 tags: - power modeling - area modeling - manycore source_file: mcpat.yml - title: CACTI url: https://github.com/HewlettPackard/cacti artifact_type: Tool categories: - Proxy Models description: Analytical model for cache and memory access time, cycle time, area, and power. fit_note: Estimates cache and memory structure costs so loops can reason about area, latency, and energy commitments. authors: N. Muralimanohar, R. Balasubramonian et al. institution: HP Labs / University of Utah order: 20 artifact_availability: source_available last_verified: 2026-07-10 tags: - cache modeling - memory modeling - power source_file: cacti.yml - title: ArchGym url: https://github.com/srivatsankrishnan/oss-arch-gym artifact_type: Tool categories: - Agentic Workflows description: Open-source gym environment for evaluating machine learning algorithms in computer architecture exploration. fit_note: Provides an ML-ready environment for comparing architecture search methods inside repeatable design loops. authors: S. Krishnan, A. Yazdanbakhsh et al. institution: Harvard / Google Research order: 21 artifact_availability: source_available last_verified: 2026-07-10 tags: - reinforcement learning - design space exploration source_file: archgym.yml - title: AutoChip url: https://github.com/shailja-thakur/AutoChip artifact_type: Tool categories: - Agentic Workflows description: Conversational hardware design using LLMs to generate Verilog from natural language specifications. fit_note: Uses simulator feedback to iteratively repair LLM-generated HDL, making rejection evidence part of the loop. authors: S. Thakur, J. Blocklove et al. institution: NYU order: 22 artifact_availability: source_available last_verified: 2026-07-10 tags: - LLMs - Verilog - automation source_file: autochip.yml - title: ChipNeMo url: https://arxiv.org/abs/2311.00176 artifact_type: Tool categories: - Agentic Workflows description: Domain-adapted LLMs for chip design, demonstrating automated EDA script generation and bug analysis. fit_note: Shows domain-adapted LLM support for chip design tasks such as code, scripts, Q&A, reports, and triage. authors: M. Liu, T. Ene et al. institution: NVIDIA order: 23 artifact_availability: paper_only last_verified: 2026-07-10 tags: - LLMs - EDA scripts - chip design source_file: chipnemo.yml - title: VeriGen url: https://arxiv.org/abs/2308.00708 artifact_type: Tool categories: - Agentic Workflows description: A large language model customized for generating functional Verilog code. fit_note: Supports RTL-generation loops by adapting language models to synthesizable Verilog code. authors: S. Thakur, B. Ahmad et al. institution: NYU / University of Calgary order: 24 artifact_availability: paper_only last_verified: 2026-07-10 tags: - LLMs - Verilog - code generation source_file: verigen.yml - title: Chisel url: https://www.chisel-lang.org/ artifact_type: Tool categories: - Data Representations description: A hardware construction language embedded in Scala that provides high-level primitives for RTL generation. fit_note: Provides a generator-based hardware representation that loops can transform, parameterize, and emit as RTL. authors: J. Bachrach, H. Vo et al. institution: UC Berkeley order: 25 artifact_availability: source_available last_verified: 2026-07-10 tags: - hardware construction - Scala - RTL source_file: chisel.yml - title: PyMTL3 url: https://github.com/pymtl/pymtl3 artifact_type: Tool categories: - Data Representations description: An open-source Python-based hardware generation and simulation framework. fit_note: Unifies modeling, simulation, and RTL generation for Python-based architecture design loops. authors: S. Jiang, P. Pan et al. institution: Cornell University order: 26 artifact_availability: source_available last_verified: 2026-07-10 tags: - Python - hardware modeling - simulation source_file: pymtl3.yml - title: FIRRTL url: https://github.com/chipsalliance/firrtl artifact_type: Tool categories: - Data Representations description: A flexible intermediate representation for RTL, serving as the bridge between high-level generators and EDA tools. fit_note: Provides an intermediate hardware representation for compiler-style transforms inside design-generation loops. authors: A. Izraelevitz, J. Koenig et al. institution: UC Berkeley / CHIPS Alliance order: 27 artifact_availability: source_available last_verified: 2026-07-10 tags: - IR - RTL - compiler infrastructure source_file: firrtl.yml - title: CocoTB url: https://github.com/cocotb/cocotb artifact_type: Tool categories: - Verification description: A coroutine-based cosimulation library for writing VHDL and Verilog testbenches in Python. fit_note: Lets loops drive HDL verification from Python testbenches and collect pass/fail evidence. authors: S. Hodgson, C. Higgs et al. institution: FOSSi Foundation / community order: 28 artifact_availability: source_available last_verified: 2026-07-10 tags: - testbenches - Python - cosimulation source_file: cocotb.yml - title: SymbiYosys url: https://symbiyosys.readthedocs.io/en/latest/ artifact_type: Tool categories: - Verification description: Front-end for Yosys-based formal verification flows, allowing agents to assert mathematical proofs against their generated RTL. fit_note: Provides formal verification checks so loops can reject RTL changes with machine-checkable evidence. authors: C. X. Wolf et al. institution: YosysHQ / community order: 29 artifact_availability: source_available last_verified: 2026-07-10 tags: - formal verification - RTL - Yosys source_file: symbiyosys.yml - title: CVDP Benchmark url: https://github.com/NVlabs/cvdp_benchmark artifact_type: Benchmark categories: - Benchmarks and Datasets description: Comprehensive Verilog Design Problems for RTL design and verification. Crucial for loops involving HDL generation and test harnesses. fit_note: Benchmarks LLM and agent performance on RTL design, verification, debugging, and specification tasks. authors: N. Pinckney, C. Deng et al. institution: NVIDIA order: 30 artifact_availability: benchmark_available last_verified: 2026-07-10 tags: - Verilog - benchmarks - verification source_file: cvdp-benchmark.yml - title: RTLLM url: https://github.com/hkust-zhiyao/RTLLM artifact_type: Benchmark categories: - Benchmarks and Datasets description: Benchmark for natural-language-to-RTL generation with Verilog designs, descriptions, and testbenches. fit_note: Benchmarks natural-language-to-RTL generation with executable testbench feedback for design agents. authors: Y. Lu, S. Liu et al. institution: HKUST order: 31 artifact_availability: benchmark_available last_verified: 2026-07-10 tags: - Verilog - LLMs - RTL generation source_file: rtllm.yml - title: RTL-Repo url: https://github.com/AUCOHL/RTL-Repo artifact_type: Dataset categories: - Benchmarks and Datasets description: Benchmark for evaluating LLMs on Verilog code completion within larger RTL repositories. fit_note: Supplies repository-scale RTL contexts for testing whether LLM loops handle multi-file hardware projects. authors: A. Allam, M. Shalan institution: AUCOHL order: 32 artifact_availability: dataset_available last_verified: 2026-07-10 tags: - Verilog - code completion - repository context source_file: rtl-repo.yml - title: MLPerf Inference url: https://github.com/mlcommons/inference artifact_type: Benchmark categories: - Benchmarks and Datasets description: MLCommons benchmark suite for measuring how fast systems run trained models across deployment scenarios. fit_note: Gives architecture loops a standardized inference benchmark target for reproducible performance evidence. authors: MLCommons contributors institution: MLCommons order: 33 artifact_availability: benchmark_available last_verified: 2026-07-10 tags: - ML systems - inference - performance source_file: mlperf-inference.yml - title: QuArch url: https://quarch.ai/ artifact_type: Benchmark categories: - Benchmarks and Datasets description: Architecture question-answering and reasoning benchmark to test if a model can reason over architecture concepts. fit_note: Tests whether AI agents understand computer-architecture concepts before they are trusted inside design loops. authors: S. Prakash, A. Cheng et al. institution: Harvard / Google Research order: 34 artifact_availability: benchmark_available last_verified: 2026-07-10 tags: - reasoning - benchmark - architecture QA source_file: quarch.yml - title: VerilogEval url: https://github.com/NVlabs/verilog-eval artifact_type: Benchmark categories: - Benchmarks and Datasets description: Specification-to-RTL and Verilog code-generation benchmark with executable checks. fit_note: Evaluates LLM Verilog generation with hardware-design tasks and automated functional checks. authors: M. Liu, N. Pinckney et al. institution: NVIDIA order: 35 artifact_availability: benchmark_available last_verified: 2026-07-10 tags: - Verilog - code generation - correctness source_file: verilogeval.yml - title: KernelBench url: https://github.com/ScalingIntelligence/KernelBench artifact_type: Benchmark categories: - Benchmarks and Datasets description: GPU-kernel generation benchmark with correctness and performance evaluation. fit_note: Benchmarks agentic kernel optimization loops with generated code, tests, and performance feedback. authors: A. Ouyang, S. Guo et al. institution: Stanford order: 36 artifact_availability: benchmark_available last_verified: 2026-07-10 tags: - GPU kernels - correctness - performance source_file: kernelbench.yml - title: CircuitNet url: https://github.com/circuitnet/CircuitNet artifact_type: Dataset categories: - Benchmarks and Datasets description: VLSI CAD dataset for machine-learning applications in EDA. fit_note: Provides VLSI CAD datasets for loops that learn or evaluate timing, congestion, and EDA prediction tasks. authors: Z. Chai, Y. Zhao et al. institution: Peking University / Wuhan University order: 37 artifact_availability: dataset_available last_verified: 2026-07-10 tags: - VLSI CAD - datasets - EDA source_file: circuitnet.yml - title: OpenROAD url: https://theopenroadproject.org/ artifact_type: Tool categories: - Physical Design description: Open-source RTL-to-GDS flow for loops that need physical-design feedback and evidence. fit_note: Supplies an open physical-design flow so loops can close the path from RTL to layout evidence. authors: T. Ajayi, V. Chhabria et al. institution: The OpenROAD Project order: 38 artifact_availability: source_available last_verified: 2026-07-10 tags: - RTL-to-GDS - physical design - open source EDA source_file: openroad.yml - title: ChiPBench url: https://openreview.net/forum?id=gDkQ5iesrI artifact_type: Benchmark categories: - Physical Design description: Benchmark focused on end-to-end physical-design impact for AI chip placement. fit_note: Benchmarks AI-based chip placement algorithms using end-to-end physical-design performance evidence. authors: Z. Wang, Z. Geng et al. institution: USTC / Alibaba order: 39 artifact_availability: paper_only last_verified: 2026-07-10 tags: - placement - physical design - benchmark source_file: chipbench.yml