gem5
Simulation
Modular computer-system simulator for architecture feedback needing workload execution and reproducible state.
Appendix C — Architecture 2.0 Resource Catalog and Links
This catalog is not a directory of links and it is not an endorsement list. Links change, tools age, and benchmark versions move. The stable question is what role a resource plays in the design loop. Does it provide workload state? Does it define valid actions? Does it return feedback? Does it expose evidence that can reject a candidate? Does it preserve provenance or negative traces?
The specific examples named below are a snapshot. The durable content is the role each resource plays; the current list of tools, datasets, and benchmarks is the kind of fast-moving record that belongs with the community forming around this topic, where it can stay current without reprinting the book. This appendix combines both the framework for judging whether a resource belongs in the loop and the current release directory of those resources.
Architecture 2.0 resource. A resource is useful for Architecture 2.0 when it makes some part of the design loop explicit, such as task, representation, environment, method role, feedback, evidence, rejection, or human decision.
Table C.1 gives a first-pass catalog. The examples are deliberately representative, not exhaustive. A reader should use the table to ask what is missing from a loop before adding another model or tool.
| Resource family | Examples | Loop role | Watch for |
|---|---|---|---|
| Architecture corpora and QA | Paper/manual corpora, DBLP-derived publication records, QuArch-style QA and reasoning data (Prakash et al. 2025b, 2025a). | Extract claim boundaries, architecture vocabulary, missing loop fields, and literature-grounded evidence limits; do not treat paper text as simulator state or rejection authority. | Paper text rarely preserves simulator state, failed candidates, tool logs, or review judgment. |
| Workloads and benchmarks | XRBench (a mobile extended reality benchmark), MLPerf (an industry-standard machine learning benchmark), and maintained benchmark suites (Kwon et al. 2023; Mattson et al. 2020; Reddi et al. 2020). | Define workload state, scenarios, metrics, rules, and comparability. | Coverage, drift, update policy, and proxy validity must remain visible. |
| Evaluation harnesses and environments | ArchGym-style environments (such as an open-source gymnasium for architecture search), benchmark harnesses, simulator wrappers, and tool-calling APIs (Krishnan et al. 2023). | Define valid actions, observations, feedback cost, logging, and rejection behavior. | A wrapper can hide tool semantics, unsupported actions, nondeterminism, and failure modes. |
| Mapping and DSE frameworks | Timeloop and MAESTRO-style mapping and dataflow tools (analytical models for accelerator evaluation) (Parashar et al. 2019; Kwon et al. 2019). | Make architecture search spaces and constraints explicit enough to explore. | Fast feedback is still a model; calibration, workload scope, and invalid candidates matter. |
| Compiler, autotuning, and codegen resources | AutoTVM, Ansor (tensor program optimizers), MLIR (a compiler infrastructure), and kernel-generation benchmarks (Chen et al. 2018; Zheng et al. 2020; Lattner et al. 2020; Ouyang et al. 2025). | Connect specialized hardware ideas to executable software paths. | A kernel, schedule, or IR result is not automatically a system-level architecture result. |
| RTL and verification benchmarks | Executable specification-to-RTL and Verilog design-problem tasks such as VerilogEval and CVDP (Comprehensive Verilog Design Problems) (datasets for hardware code generation); see the live links below. | Test method claims against compile, simulation, and verification feedback. | Passing a small HDL task is not the same as closing an architecture loop. |
| Full-system simulation and hardware/software harnesses | gem5 (a modular full-system simulator), FireSim (an FPGA-accelerated simulation platform), Chipyard (an integrated SoC design framework), and related harnesses (Binkert et al. 2011; Karandikar et al. 2018; Amid et al. 2020). | Connect workload execution, software stacks, generated hardware, and stronger feedback. | Setup state, versions, nondeterminism, and workload coverage must be recorded. |
| Physical-design and EDA evidence | OpenROAD’s open RTL-to-GDS flow, CircuitNet (an open-source dataset for machine learning in EDA), ChiPBench (a benchmark for physical design), and placement or signoff-adjacent artifacts (Chai et al. 2022; Wang et al. 2025). | Give physical constraints authority to reject architecture candidates. | Intermediate scores can mislead unless tied to downstream timing, area, power, or routability. |
| Benchmark governance and roadmaps | MLCommons rules, SPEC (Standard Performance Evaluation Corporation) suites, and roadmaps in the style of the International Roadmap for Devices and Systems (IRDS). | Maintain comparability, versioning, scenario definitions, and long-horizon evidence needs. | Governance is part of the loop; stale rules or hidden updates change what claims mean. |
| Evidence and provenance artifacts | Design-loop cards, evidence ledgers, source records, seeds, configs, tool logs, calibration records, and negative traces. | Make claims auditable, reproducible, rejectable, and reusable. | These records are often uncodified, private, or discarded because they are not publication artifacts. |
Prakash, Shvetank et al. 2025b. “QuArch: A Question-Answering Dataset for AI Agents in Computer Architecture.” IEEE Computer Architecture Letters, ahead of print. https://doi.org/10.1109/LCA.2025.3541961.
Prakash, Shvetank et al. 2025a. QuArch: A Benchmark for Evaluating LLM Reasoning in Computer Architecture. https://arxiv.org/abs/2510.22087.
Kwon, Hyoukjun et al. 2023. “XRBench: An Extended Reality (XR) Machine Learning Benchmark Suite for the Metaverse.” Proceedings of Machine Learning and Systems.
Mattson, Peter, Hanlin Tang, Gu-Yeon Wei, et al. 2020. “MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance.” IEEE Micro 40 (2): 8–16. https://doi.org/10.1109/MM.2020.2974843.
Reddi, Vijay Janapa, Christine Cheng, David Kanter, et al. 2020. “MLPerf Inference Benchmark.” 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), 446–59. https://doi.org/10.1109/ISCA45697.2020.00045.
Krishnan, Srivatsan et al. 2023. “ArchGym: An Open-Source Gymnasium for Machine Learning Assisted Architecture Design.” Proceedings of the 50th Annual International Symposium on Computer Architecture, ISCA ’23. https://doi.org/10.1145/3579371.3589049.
Parashar, Angshuman, Priyanka Raina, Yakun Sophia Shao, et al. 2019. “Timeloop: A Systematic Approach to DNN Accelerator Evaluation.” 2019 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS, 304–15. https://doi.org/10.1109/ISPASS.2019.00042.
Kwon, Hyoukjun, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, and Tushar Krishna. 2019. “Understanding Reuse, Performance, and Hardware Cost of DNN Dataflows: A Data-Centric Approach.” Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO ’52, 754–68. https://doi.org/10.1145/3352460.3358252.
Chen, Tianqi, Lianmin Zheng, Eddie Yan, et al. 2018. “Learning to Optimize Tensor Programs.” Advances in Neural Information Processing Systems 31.
Zheng, Lianmin et al. 2020. “Ansor: Generating High-Performance Tensor Programs for Deep Learning.” 14th USENIX Symposium on Operating Systems Design and Implementation, 863–79.
Lattner, Chris, Mehdi Amini, Uday Bondhugula, et al. 2020. “MLIR: A Compiler Infrastructure for the End of Moore’s Law.” arXiv Preprint arXiv:2002.11054, ahead of print. https://doi.org/10.48550/arXiv.2002.11054.
Ouyang, Anne, Simon Guo, Simran Arora, et al. 2025. “KernelBench: Can LLMs Write Efficient GPU Kernels?” arXiv Preprint arXiv:2502.10517, ahead of print. https://doi.org/10.48550/arXiv.2502.10517.
Binkert, Nathan, Bradford Beckmann, Gabriel Black, et al. 2011. “The Gem5 Simulator.” ACM SIGARCH Computer Architecture News 39 (2): 1–7. https://doi.org/10.1145/2024716.2024718.
Karandikar, Sagar, Howard Mao, Donggyu Kim, et al. 2018. “FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.” 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), 29–42. https://doi.org/10.1109/ISCA.2018.00014.
Amid, Alon, David Biancolin, Abraham Gonzalez, et al. 2020. “Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.” IEEE Micro 40 (4): 10–21. https://doi.org/10.1109/MM.2020.3013233.
Chai, Zhuomin, Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, and Ru Huang. 2022. “CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA).” Science China Information Sciences, ahead of print. https://doi.org/10.1007/s11432-022-3571-8.
Wang, Zhihai et al. 2025. “Benchmarking End-to-End Performance of AI-Based Chip Placement Algorithms.” Advances in Neural Information Processing Systems (NeurIPS). https://arxiv.org/abs/2407.15026.
C.1 Use the Catalog as a Loop Checklist
The catalog is most useful when it is used as a checklist. For a new Architecture 2.0 project, choose one resource for each role:
- a workload or benchmark that defines the task boundary;
- a representation that records the state the loop can read and change;
- an environment or harness that defines valid actions and observations;
- a feedback source with an explicit latency, fidelity, and cost model;
- an evidence ledger that preserves configurations, assumptions, and negative traces;
- rejection authority and a human decision owner.
If one of these fields is missing, the loop may still be useful, but its claim should be bounded accordingly. A paper-reading tool can help identify claim boundaries, missing workload records, absent negative traces, and unsupported commitments even if it cannot act on RTL. A simulator environment can support design-space exploration even if it cannot validate timing closure. A kernel-generation benchmark can reveal code-generation capability even if it does not prove system-level efficiency.
Lighthouse prompt: Use the catalog to fill the Lighthouse loop
Context. The catalog becomes a checklist only when every Lighthouse fragment has a resource that can carry it.
In the Lighthouse prompt. “XRBench-class real-time mobile XR workload” anchors the workload family, while the loop must still pin the scenario, version, inputs, latency target, software stack, and coverage. Architecture parameters and workload traces supply representation. A simulator or cost-model wrapper supplies legal actions and observations.
Resource map. Compiler/runtime resources test the “64-bit RISC-V-based” ISA/ABI, vector path, driver or runtime API, library integration, and fallbacks. Full-system or SoC harnesses test integration, coherence, and data movement. EDA, PDK, and library evidence can test implementation feasibility under the “3 W TDP target in a 3 nm-class LP mobile process.” Verification resources test correctness, corner cases, and reliability assumptions. A card or ledger turns the “design-space report with evidence and rejected alternatives” into a concrete evidence ledger with a human owner.
Takeaway. An empty row does not make the loop useless; it bounds the claim the loop is allowed to make.
C.2 Missing Infrastructure
The most important future resources are not only larger corpora. Architecture needs shared records of design-loop state:
- negative-trace repositories that preserve failed candidates and reasons;
- environment schemas that state actions, observations, costs, and invalid states;
- benchmark-update protocols that record drift and version changes;
- confidentiality-preserving ways to share tool traces and design reviews;
- standard design-loop cards for papers, artifacts, and design reviews.
These resources would make the field more reviewable and more cumulative. They would also make AI-assisted architecture work easier to evaluate, because the community could ask whether a method improved the loop rather than merely whether it produced a plausible artifact. The sections below keep the moving list of concrete links organized by these roles.
C.3 Live Resource Directory
These links are not a general computer-architecture, pedagogy, or reproducibility directory. A resource earns space here only if it is directly useful for AI-mediated architecture work, such as naming a task, representing state, exposing actions, returning feedback, preserving evidence, or rejecting a result. Use the list as a starting point and check current versions before relying on any benchmark, dataset, simulator, or tool. This directory uses live links rather than formal bibliography entries; cite the primary paper or project artifact when making a scholarly claim.
C.4 Architecture 2.0 Framing
- Essay: Architecture 2.0 gymnasium essay. Intent-level framing for why architecture needs data-centric environments rather than isolated model demonstrations. — title: “Architecture 2.0 Resources and Tool Catalog” listing:
- id: tool-catalog contents: tools.yml type: grid categories: true filter-ui: true sort-ui: false fields: [title, description, categories] —
The most important metric for an open-source project is the number of people who use it to build something the original authors never anticipated.
— Unknown, open-source adage
Author’s Note: The ecosystem of AI tools for computer architecture and hardware/software co-design is moving faster than any static text can capture. The catalog below is a living document. We invite the community to submit new proxy models, simulators, AI-assisted workflows, and benchmarks to the Architecture 2.0 GitHub Repository.
This appendix is not a bibliography. It is an index of Architecture 2.0 building blocks: the simulators, proxy models, verification harnesses, and data representations that provide the State, Action, and Rejection surfaces required to build AI-assisted design loops.
If you are building an AI-assisted workflow, you will likely need to piece together tools from multiple categories below.
C.5 The Living Tool Catalog
Below is a searchable, filterable grid of community-submitted resources that enable Architecture 2.0.
No matching items
C.6 Architecture 2.0 Templates and Artifacts
Design-loop card and review rubric: Appendix B. Use the core card and its contextual adaptations to review a paper, proposal, research artifact, or internal loop before trusting its architectural claim.
Blank design-loop template: Table B.6. Use the blank card as a one-page handout for paper reviews, project proposals, and design reviews.
C.7 Using and Citing the Preview
Use this preview as a working vocabulary for paper reviews, project proposals, class discussions, and internal design reviews. For citation, cite the preview URL and version when referring to this book directly, and cite the Architecture 2.0 foundations article when referring to the broader vision and autonomy framing.
For feedback on the preview, or to submit a tool to the catalog above, visit the Architecture 2.0 GitHub Repository.